The present invention relates to a cell signal processing circuit and an optical switch apparatus using the same, and in more detail, to a processing circuit which processes input signals divided into cells each including a constant number of bits in a time series and an optical switch apparatus composed of the processing circuit, particularly a structure of a timing recovery and cell synchronization unit.
An asynchronous transfer mode (ATM) is regarded as a future wide band switching system, wherein a signal is divided into constant bit number units each referred to as a "cell", to which information indicative of a destination or the like called "header" is added at the head thereof, and a switch array decodes the header and distributes respective cells to respective destinations to thereby perform a switching operation. For a high speed switching of such cells, utilization of a wide band and a high speed possessed by optical features is thought to be effective.
For example, "A Photonic Approach to ATM Switching" by Amada et al presented at Global Telecommunications Conference '89 (GLOBECOM '89), No. 50.2, Dallas, Tex., November, 1989 and "A Packet Switch Architecture Using An Optical Switch Array" by Amada, et al. published in documents of Society for Technological Research of Electronics, Information and Communication Academy, SSE88-95, 1988, pp. 25-30 has realized an optical ATM apparatus by using an optical switch array in a switching stage.
Since it is difficult to realize functions, such as a memory function for buffering cells and a logical processing function for processing the header, of the above-mentioned ATM switch apparatus by present optical devices, an optical switching stage (optical switch array) 8 only is composed of an optical device, and an electric-photo converter 6 and an photoelectric converter 9 are respectively provided to input and output sections thereof such that the remaining arrangement is formed by electric circuits as shown in FIG. 7. Specifically, as shown in FIG. 8A, an electric input signal a in a cell time series is once stored in an input buffer 3 and waits for a switch control. When a read permission is issued, data is read from the input buffer by a signal from a read control unit 2, and converted to an optical signal by an electric-photo converter 6 to constitute an optical input signal to the optical switch array 8. Since the optical switch array 8 is not provided with a memory function, data is lacked when the optical switch 8 is changed over. To prevent this data loss, a dummy signal (non-signal condition) is added between adjacent cells before the cell signals are converted to optical signals, as shown in FIG. 8B. The optical switch array 8 is changed over by an optical switch driving signal, the change-over timing of which is located at a substantial center of the dummy signal, as shown in FIG. 8C, to thereby prevent loss of data signals to be exchanged.
An optical signal outputted from the optical switch array 8 is converted to an electric signal by the photoelectric converter 9 on an output port side, once stored into an output buffer 22 and then outputted in accordance with a control signal from a read control unit 23. For this reason, a bit drop never occurs in signals to be exchanged except for the dummy signals, that is, in the cells.
It is necessary to provide an actual apparatus with a decision circuit, a clock (timing) recovery circuit, a cell synchronization circuit and the like on the output side of the optical switch array 8 prior to the input of the output buffer 22. A phase matching is important, particularly for a high speed signal processing. If cell synchronizing signals are individually formed and distributed to a plurality of output sections of a switch array, the phase matching is quite difficult. A simultaneous transmission by the use of a wavelength multiplex or the like requires a wavelength exclusively assigned thereto and optical parts such as a wavelength filter, which results in an increase of an insertion loss. For this reason, it is necessary to extract the cell synchronizing signals from the output of the switch array.
The identification circuit is adapted to extract a clock signal from an electric signal by the clock recovery circuit and comprises a circuit which performs a decision and reshaping by means of a decision for regenerating the foregoing amplified electric signal with the clock signal used as a decision timing. In this structure, the identifier and the amplifier are connected so as to block direct current components.
The above-mentioned conventional technology does not particularly consider the dummy signal with respect to a signal form. For this reason, an ordinary photoelectric conversion unit, if used, may cause loss of the dummy signal, which incurs problems when a signal decision and a timing recovery are performed on the output side. The first problem is that signal loss causes fluctuations in a mark density of received data, which leads to a deterioration in a decision sensitivity. The second problem is that the timing recovery circuit may possibly malfunction due to a changing point of a signal level caused by the signal loss.